TY  - GEN
AU  - Tejswi A EDM12B006
AU  - 
TI  - Design and Implementation of phase locked loop for power applications
PY  - 2016///
CY  - IIITDM Kancheepuram
PB  - Department of Electronics Engineering - Design and Manufacturing
KW  - loop
N1  - B.Tech Theses
ER  -