Enabling in memory computing with energy efficient memory architecture for AI hardware accelerators
Kavitha S
Enabling in memory computing with energy efficient memory architecture for AI hardware accelerators - Chennai ECE 2025
AI hardware accelerators
This system level innovation is vital for supporting the high data rates required by modern artificial intelligence hardware accelerators ensuring communication between various components of a computer system.
Static random access memory; in memory computing; arithmetic and logic operations; DNA sequence alignment; cryptography; high speed memory interconnects
621.3 KAV
Enabling in memory computing with energy efficient memory architecture for AI hardware accelerators - Chennai ECE 2025
AI hardware accelerators
This system level innovation is vital for supporting the high data rates required by modern artificial intelligence hardware accelerators ensuring communication between various components of a computer system.
Static random access memory; in memory computing; arithmetic and logic operations; DNA sequence alignment; cryptography; high speed memory interconnects
621.3 KAV